module ysyx_050369_if (
    input               clk,
    input               rst,
    input       [31:0]  pc_reg,
    input               if_valid,
    input               i_pc_stop,
    input       [31:0]  pre_pc,
    input               pre_jump,
    input               i_ctrl_pc_error,
    input               i_ex_fence_i,
    input               dc_fdone,
    output              if2id_valid,
    output      [31:0]  o_inst,
    output      [31:0]  o_pc_reg,
    output      [31:0]  o_pre_pc,
    output              o_pre_jump,
    output              o_icache_stop,
`ifdef ysyx_050369_SOC
    output [5:0]    io_sram4_addr,
	output          io_sram4_cen,
	output          io_sram4_wen,
	output [127:0]  io_sram4_wmask,
	output [127:0]  io_sram4_wdata,
	input [127:0]   io_sram4_rdata,
	output [5:0]    io_sram5_addr,
	output          io_sram5_cen,
	output          io_sram5_wen,
	output [127:0]  io_sram5_wmask,
	output [127:0]  io_sram5_wdata,
	input [127:0]   io_sram5_rdata,
    output [5:0]    io_sram6_addr,
	output          io_sram6_cen,
	output          io_sram6_wen,
	output [127:0]  io_sram6_wmask,
	output [127:0]  io_sram6_wdata,
	input [127:0]   io_sram6_rdata,
    output [5:0]    io_sram7_addr,
	output          io_sram7_cen,
	output          io_sram7_wen,
	output [127:0]  io_sram7_wmask,
	output [127:0]  io_sram7_wdata,
	input [127:0]   io_sram7_rdata,
`endif
    input  [127:0]  cache_wdata,
    input           cache_wen,
    output          axi_read,
    output          unbrust,
    output [31:0]   ic_raddr

    
);
    wire flush;
    assign if2id_valid = if_valid;
    assign flush       = i_ex_fence_i || i_ctrl_pc_error && (~o_icache_stop);
    
ysyx_050369_icache icache(
	.clk        (clk),    // Clock
	.rst        (rst),  // Asynchronous reset active low
    .pc         (pc_reg),
    .pc_stop    (o_icache_stop),
    .i_stop     (i_pc_stop),    
    .fulsh      (flush),
    .dc_fdone   (dc_fdone),
    .i_pre_pc   (pre_pc),
    .i_pre_jump (pre_jump),
    .o_pre_pc   (o_pre_pc),
    .o_pre_jump (o_pre_jump),
    .o_inst     (o_inst),
	.o_pc       (o_pc_reg),
`ifdef ysyx_050369_SOC
    .io_sram4_addr  (io_sram4_addr),
    .io_sram4_cen   (io_sram4_cen),
    .io_sram4_wen   (io_sram4_wen),
    .io_sram4_wmask (io_sram4_wmask),
    .io_sram4_wdata (io_sram4_wdata),
    .io_sram4_rdata (io_sram4_rdata),
    .io_sram5_addr  (io_sram5_addr),
    .io_sram5_cen   (io_sram5_cen),
    .io_sram5_wen   (io_sram5_wen),
    .io_sram5_wmask (io_sram5_wmask),
    .io_sram5_wdata (io_sram5_wdata),
    .io_sram5_rdata (io_sram5_rdata),
    .io_sram6_addr  (io_sram6_addr),
    .io_sram6_cen   (io_sram6_cen),
    .io_sram6_wen   (io_sram6_wen),
    .io_sram6_wmask (io_sram6_wmask),
    .io_sram6_wdata (io_sram6_wdata),
    .io_sram6_rdata (io_sram6_rdata),
    .io_sram7_addr  (io_sram7_addr),
    .io_sram7_cen   (io_sram7_cen),
    .io_sram7_wen   (io_sram7_wen),
    .io_sram7_wmask (io_sram7_wmask),
    .io_sram7_wdata (io_sram7_wdata),
    .io_sram7_rdata (io_sram7_rdata),
`endif 
    .cache_wdata    (cache_wdata),
    .cache_wen      (cache_wen),
    .axi_read       (axi_read),
    .unbrust        (unbrust),
    .ic_raddr       (ic_raddr)
);

endmodule